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1-49 h intelligent power module and gate drive interface optocouplers technical data features ? performance specified for common ipm applications over industrial temperature range: -40 c to 100 c ? fast maximum propagation delays t phl = 400 ns t plh = 550 ns ? minimized pulse width distortion (pwd = 450 ns) ? 15 kv/ m s minimum common mode transient immunity at v cm = 1500 v ? ctr > 44% at i f = 10 ma ? safety approval ul recognized - 2500 v rms for 1 minute (5000 v rms for 1 minute for hcnw4506 and hcpl-4506 option 020) per ul1577 csa approved vde 0884 approved -v iorm = 630 v peak for hcpl-4506 option 060 -v iorm = 1414 v peak for hcnw4506 bsi certified (hcnw4506) applications ? ipm isolation ? isolated igbt/mosfet gate drive ? ac and brushless dc motor drives ? industrial inverters description the hcpl-4506 and hcpl-0466 contain a gaasp led while the hcnw4506 contains an algaas led. the led is optically coupled to an integrated high gain photo detector. minimized propa- the connection of a 0.1 m f bypass capacitor between pins 5 and 8 is recommended. gation delay difference between devices make these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. an on chip 20 k w output pull-up resistor can be enabled by short- ing output pins 6 and 7, thus eliminating the need for an external pull-up resistor in common ipm applications. speci- fications and performance plots are given for typical ipm applications. hcpl-4506 hcpl-0466 hcnw4506 functional diagram truth table led v o on l off h 8 7 6 1 3 shield 5 2 4 20 k w nc anode cathode nc v cc v l v o gnd caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. selection guide operating temperature t a [ c] single channel packages 8-pin dip small outline widebody min. max. (300 mil) so-8 (400 mil) hermetic* -40 100 hcpl-4506 hcpl-0466 hcnw4506 -55 125 hcpl-5300 hcpl-5301 *technical data for these products are on separate hp publications. 5965-3603e
1-50 0.635 ?0.25 (0.025 ?0.010) 12?nom. 9.65 ?0.25 (0.380 ?0.010) 0.635 ?0.130 (0.025 ?0.005) 7.62 ?0.25 (0.300 ?0.010) 5 6 7 8 4 3 2 1 9.65 ?0.25 (0.380 ?0.010) 6.350 ?0.25 (0.250 ?0.010) 1.016 (0.040) 1.194 (0.047) 1.194 (0.047) 1.778 (0.070) 9.398 (0.370) 9.906 (0.390) 4.826 (0.190) typ. 0.381 (0.015) 0.635 (0.025) pad location (for reference only) 1.080 ?0.320 (0.043 ?0.013) 4.19 (0.165) max. 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 9.65 ?0.25 (0.380 ?0.010) 1.78 (0.070) max. 1.19 (0.047) max. hp xxxxz yyww date code 1.080 ?0.320 (0.043 ?0.013) 2.54 ?0.25 (0.100 ?0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 5?typ. option code* ul recognition ur 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 ?0.25 (0.300 ?0.010) type number * marking code letter for option numbers. "l" = option 020 "v" = option 060 option numbers 300 and 500 not marked. 6.35 ?0.25 (0.250 ?0.010) package outline drawings figure 2. hcpl-4506 gull wing surface mount option #300 outline drawing. figure 1. hcpl-4506 outline drawing (standard dip package). ordering information specify part number followed by option number (if desired). example: hcpl-4506#xxx 020 = ul 5000 v rms/1 minute option* 060 = vde 0884 v iorm = 630 v peak option* 300 = gull wing surface mount option? 500 = tape and reel packaging option option data sheets are available. contact your hewlett-packard sales representative or authorized distributor for information. * for hcpl-4506 only. combination of option 020 and option 060 is not available. ?gull wing surface mount option applies to through hole parts only.
1-51 1.00 ?0.15 (0.039 ?0.006) 7?nom. 12.30 ?0.30 (0.484 ?0.012) 0.75 ?0.25 (0.030 ?0.010) 11.00 (0.433) 5 6 7 8 4 3 2 1 11.15 ?0.15 (0.442 ?0.006) 9.00 ?0.15 (0.354 ?0.006) 1.3 (0.051) 12.30 ?0.30 (0.484 ?0.012) 6.15 (0.242) typ. 0.9 (0.035) pad location (for reference only) 1.78 ?0.15 (0.070 ?0.006) 4.00 (0.158) max. 1.55 (0.061) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) max. 5 6 7 8 4 3 2 1 11.15 ?0.15 (0.442 ?0.006) 1.78 ?0.15 (0.070 ?0.006) 5.10 (0.201) max. 1.55 (0.061) max. 2.54 (0.100) typ. dimensions in millimeters (inches). 7?typ. 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) 11.00 (0.433) 9.00 ?0.15 (0.354 ?0.006) max. 10.16 (0.400) typ. hp hcnwxxxx yyww date code type number 0.51 (0.021) min. 0.40 (0.016) 0.56 (0.022) 3.10 (0.122) 3.90 (0.154) xxx yww 8765 4 3 2 1 5.842 ?0.203 (0.236 ?0.008) 3.937 ?0.127 (0.155 ?0.005) 0.381 ?0.076 (0.016 ?0.003) 1.270 (0.050) bsg 5.080 ?0.127 (0.200 ?0.005) 3.175 ?0.127 (0.125 ?0.005) 1.524 (0.060) 45?x 0.432 (0.017) 0.228 ?0.025 (0.009 ?0.001) type number (last 3 digits) date code 0.305 (0.012) min. dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). 0.152 ?0.051 (0.006 ?0.002) 7 figure 3. hcpl-0466 outline drawing (8-pin small outline package). figure 4a. hcnw4506 outline drawing (8-pin widebody package). pin location (for reference only) figure 4b. hcnw4506 outline drawing (8-pin widebody package with gull wing surface mount option 300).
1-52 insulation and safety related specifications 8-pin dip widebody (300 mil) so-8 (400 mil) parameter symbol value value value units conditions minimum external l(101) 7.1 4.9 9.6 mm measured from input terminals air gap (external to output terminals, shortest clearance) distance through air. minimum external l(102) 7.4 4.8 10.0 mm measured from input terminals tracking (external to output terminals, shortest creepage) distance path along body. minimum internal 0.08 0.08 1.0 mm through insulation distance, plastic gap conductor to conductor, usually (internal clearance) the direct distance between the photoemitter and photodetector inside the optocoupler cavity. minimum internal na na 4.0 mm measured from input terminals tracking (internal to output terminals, along creepage) internal cavity. tracking resistance cti 200 200 200 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia iiia iiia material group (din vde 0110, 1/89, table 1) option 300 - surface mount classification is class a in accordance with cecc 00802. regulatory information the devices contained in this data sheet have been approved by the following organizations: ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca 88324. vde approved according to vde 0884/06.92 (hcnw4506 and hcpl-4506 option 060 only). bsi certification according to bs451:1994 (bs en60065:1994); bs en60950:1992 (bs7002:1992) and en41003:1993 for class ii applications (hcnw4506 only). note: use of nonchlorine activated fluxes is recommended. 240 d t = 115?, 0.3?/sec 0 d t = 100?, 1.5?/sec d t = 145?, 1?/sec time ?minutes temperature ?? 220 200 180 160 140 120 100 80 60 40 20 0 260 123 456789101112 solder reflow temperature profile
1-53 vde 0884 insulation related characteristics (hcpl-4506 option 060 only) description symbol characteristic units installation classification per din vde 0110/1.89, table 1 for rated mains voltage 300 v rms i-iv for rated mains voltage 450 v rms i-iii climatic classification 55/100/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 630 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, v pr 1181 v peak partial discharge < 5 pc input to output test voltage, method a* v iorm x 1.5 = v pr , type and sample test, v pr 945 v peak t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage* (transient overvoltage, t ini = 10 sec) v iotm 6000 v peak safety limiting values (maximum values allowed in the event of a failure, also see figure 18, thermal derating curve.) case temperature t s 175 c input current i s,input 230 ma output power p s,output 600 mw insulation resistance at t s , v io = 500 v r s 3 10 9 w vde 0884 insulation related characteristics (hcnw4506 only) description symbol characteristic units installation classification per din vde 0110/1.89, table 1 for rated mains voltage 600 v rms i-iv for rated mains voltage 1000 v rms i-iii climatic classification 55/100/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 1414 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, v pr 2652 v peak partial discharge < 5 pc input to output test voltage, method a* v iorm x 1.5 = v pr , type and sample test, v pr 2121 v peak t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage* (transient overvoltage, t ini = 10 sec) v iotm 8000 v peak safety limiting values (maximum values allowed in the event of a failure, also see figure 18, thermal derating curve.) case temperature t s 150 c input current i s,input 400 ma output power p s,output 700 mw insulation resistance at t s , v io = 500 v r s 3 10 9 w *refer to the front of the optocoupler section of the current catalog, under product safety regulations section (vde 0884), for a detailed description. note: isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circu its in application.
1-54 electrical specifications over recommended operating conditions unless otherwise specified: t a = -40 c to +100 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off) = -5 v to 0.8 v? parameter symbol min. typ.* max. units test conditions fig. note current transfer ratio ctr 44 90 % i f = 10 ma, v o = 0.6 v 5 low level output current i ol 4.4 9.0 ma i f = 10 ma, v o = 0.6 v 5,6 low level output voltage v ol 0.3 0.6 v i o = 2.4 ma input threshold current i th 1.5 5.0 ma v o = 0.8 v, i o = 0.75 ma 5 14 high level output current i oh 550 m av f = 0.8 v 7 high level supply current i cch 0.6 1.3 ma v f = 0.8 v, v o = open 14 low level supply current i ccl 0.6 1.3 ma i f = 10 ma, v o = open 14 input forward voltage v f 1.5 1.8 v hcpl-4506 i f = 10 ma 8 hcpl-0466 1.6 1.85 hcnw4506 9 temperature coefficient d v f / d t a -1.6 mv/ c hcpl-4506 i f = 10 ma of forward voltage hcpl-0466 -1.3 hcnw4506 input reverse breakdown bv r 5 v hcpl-4506 i r = 100 m a voltage hcpl-0466 3 hcnw4506 input capacitance c in 60 pf hcpl-4506 f = 1 mhz, hcpl-0466 v f = 0 v 72 hcnw4506 internal pull-up resistor r l 14 20 25 k w t a = 25 c10,11 internal pull-up resistor d r l / d t a 0.014 k w / c temperature coefficient *all typical values at 25 c, v cc = 15 v. ?v f(off) = -3 v to 0.8 v for hcnw4506. recommended operating conditions parameter symbol min. max. units power supply voltage v cc 4.5 30 volts output voltage v o 0 30 volts input current (on) i f(on) 10 20 ma input voltage (off) v f(off) * -5 0.8 v operating temperature t a -40 100 c *recommended v f(off) = -3 v to 0.8 v for hcnw4506. absolute maximum ratings parameter symbol min. max. units storage temperature t s -55 125 c operating temperature t a -40 100 c average input current [1] i f(avg) 25 ma peak input current [2] (50% duty cycle, 1 ms pulse width) i f(peak) 50 ma peak transient input current (<1 m s pulse width, 300 pps) i f(tran) 1.0 a reverse input voltage (pin 3-2) hcpl-4506, hcpl-0466 v r 5 volts hcnw4506 3 average output current (pin 6) i o(avg) 15 ma resistor voltage (pin 7) v 7 -0.5 v cc volts output voltage (pin 6-5) v o -0.5 30 volts supply voltage (pin 8-5) v cc -0.5 30 volts output power dissipation [3] p o 100 mw total power dissipation [4] p t 145 mw lead solder temperature (hcpl-4506) 260 c for 10 s, 1.6 mm below seating plane lead solder temperature (hcnw4506) 260 c for 10 s (up to seating plane) infrared and vapor phase reflow temperature see package outline drawings section (hcpl-0466 and option 300)
1-55 switching specifications (r l = 20 k w external) over recommended operating conditions unless otherwise specified: t a = -40 c to +100 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off) = -5 v to 0.8 v? parameter symbol min. typ.* max. units test conditions fig. note propagation delay t phl i f(on) = 10 ma, 10, 9, time to low v f(off) = 0.8 v, 12, 12, output level 14-17 14 propagation delay t plh time to high output level pulse width pwd 200 450 ns c l = 100 pf 18 distortion propagation delay t plh -t phl -150 200 450 ns 15 difference between any 2 parts output high level |cm h |15 30 kv/ m si f = 0 ma, v cc = 15.0 v, 11 16 common mode v o > 3.0 v c l = 100 pf, transient immunity v cm = 1500 v p-p output low level |cm l |15 30 kv/ m si f = 10 ma 17 common mode v o < 1.0 v transient immunity switching specifications (r l = internal pull-up) over recommended operating conditions unless otherwise specified: t a = -40 c to +100 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off) = -5 v to 0.8 v? parameter symbol min. typ.* max. units test conditions fig. note propagation delay t phl 20 200 400 ns i f(on) = 10 ma, v f(off) = 0.8 v, 10, 9-12, time to low v cc = 15.0 v, c l = 100 pf, 13 14 output level v thlh = 2.0 v, v thhl = 1.5 v propagation delay t plh 220 450 650 ns time to high output level pulse width pwd 250 500 ns 18 distortion propagation delay t plh -t phl -150 250 500 ns 15 difference between any 2 parts output high level |cm h |30 kv/ m si f = 0 ma, v cc = 15.0 v, 11 16 common mode v o > 3.0 v c l = 100 pf, transient immunity v cm = 1500 v p-p , output low level |cm l | 30 kv/ m si f = 16 ma, 17 common mode v o < 1.0 v transient immunity power supply psr 1.0 v p-p square wave, t rise , t fall 14 rejection > 5 ns, no bypass capacitors *all typical values at 25 c, v cc = 15 v. ?v f(off) = -3 v to 0.8 v for hcnw4506. v cc = 15.0 v, v thlh = 2.0 v, v thhl = 1.5 v 130 c l = 10 pf 30 200 400 ns c l = 100 pf 100 ns c l = 10 pf 270 400 550 ns c l = 100 pf t a = 25 c t a = 25 c
1-56 package characteristics over recommended temperature (t a = -40 c to 100 c) unless otherwise specified. parameter sym. min. typ.* max. units test conditions fig. note input-output momentary v iso 2500 v rms hcpl-4506 rh < 50%, 6, 7, 8 withstand voltage ? hcpl-0466 t = 1 min. 5000 hcnw4506 6, 8, 13 option 020 5000 hcnw4506 6, 8 resistance r i-o 10 12 w hcpl-4506 v i-o = 500 vdc 6 (input-output) hcpl-0466 10 12 10 13 hcnw4506 capacitance c i-o 0.6 pf hcpl-4506 f = 1 mhz 6 (input-output) hcpl-0466 0.5 hcnw4506 * all typical values at 25 c, v cc = 15 v. ?the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to the vde 0884 insulation related characteristics table (if applicable), your equipment level safety specification or hp application note 1074 entitled optocoupler input-output endurance voltage, publication number 5963-2203e. notes: 1. derate linearly above 90 c free-air temperature at a rate of 0.8 ma/ c. 2. derate linearly above 90 c free-air temperature at a rate of 1.6 ma/ c. 3. derate linearly above 90 c free-air temperature at a rate of 3.0 mw/ c. 4. derate linearly above 90 c free-air temperature at a rate of 4.2 mw/ c. 5. current transfer ratio in percent is defined as the ratio of output collector current (i o ) to the forward led input current (i f ) times 100. 6. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 7. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 3 3000 v rms for 1 second (leakage detection current limit, i i-o 5 m a). this test is performed before the 100% production test shown in the vde 0884 insulation related characteristics table, if applicable. 8. for option 020, in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 3 6000 v rms for 1 second (leakage detection current limit, i i-o 5 m a). this test is performed before the 100% production test for partial discharge (method b) shown in the vde 0884 insulation related characteristics table, if applicable. 9. pulse: f = 20 khz, duty cycle = 10%. 10. the internal 20 k w resistor can be used by shorting pins 6 and 7 together. 11. due to tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved by using an external 20 k w 1% load resistor. for more information on how propagation delay varies with load resistance, see figure 12. 12. the r l = 20 k w , c l = 100 pf load represents a typical ipm (intelligent power module) load. 13. see option 020 data sheet for more information. 14. use of a 0.1 m f bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise. 15. the difference between t plh and t phl between any two devices under the same test condition. (see ipm dead time and propagation delay specifications section.) 16. common mode transient immunity in a logic high level is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a logic high state (i.e., v o > 3.0 v). 17. common mode transient immunity in a logic low level is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a logic low state (i.e., v o < 1.0 v). 18. pulse width distortion (pwd) is defined as |t phl - t plh | for any given device. t a = 25 c
1-57 figure 8. hcpl-4506 and hcpl-0466 input current vs. forward voltage. figure 9. hcnw4506 input current vs. forward voltage. figure 6. normalized output current vs. temperature. figure 5. typical transfer characteristics. figure 7. high level output current vs. temperature. figure 10. propagation delay test circuit. i o ?output current ?ma 0 i f ?forward led current ?ma 6 4 2 5 10 10 15 20 v o = 0.6 v 8 0 100 ? 25 ? -40 ? normalized output current t a ?temperature ?? 0.95 0.90 0.85 0 40 60 100 i f = 10 ma v o = 0.6 v 1.00 -40 -20 20 80 1.05 0.80 i f ?forward current ?ma 1.10 0.001 v f ?forward voltage ?volts 1.60 10 1.0 0.1 1.20 1000 1.30 1.40 1.50 t a = 25? i f v f + 0.01 100 0.1 ? v cc = 15 v 20 k w i f(on) =10 ma v out c l * + *total load capacitance + i f v o v thhl t phl t plh t f t r 90% 10% 90% 10% v thlh 8 7 6 1 3 shield 5 2 4 5 v 20 k w i f ?input forward current ?ma 0.001 v f ?input forward voltage ?v 1 0.1 0.01 1.0 100 1.4 1.8 2.0 t a = 25 ? 10 0.8 1.2 1.6 i f v f + i oh ?high level output current ?? t a ?temperature ?? 15.0 10.0 5.0 0 40 60 100 20.0 -40 -20 20 80 0 4.5 v 30 v v f = 0.8 v v cc = v o = 4.5 v or 30 v
1-58 figure 12. propagation delay with external 20 k w rl vs. temperature. figure 13. propagation delay with internal 20 k w rl vs. temperature. figure 14. propagation delay vs. load resistance. figure 11. cmr test circuit. typical cmr waveform. figure 17. propagation delay vs. input current. figure 15. propagation delay vs. load capacitance. figure 16. propagation delay vs. supply voltage. 0.1 ? v cc = 15 v 20 k w a i f v out 100 pf* + *100 pf total capacitance + + b v ff v cm = 1500 v 8 7 6 1 3 shield 5 2 4 20 k w v cm d t ov v o v o switch at a: i f = 0 ma switch at b: i f = 10 ma v cc v ol v cm d t d v d t = t p ?propagation delay ?ns t a ?temperature ?? 400 300 200 0 40 60 100 500 -40 -20 20 80 t plh t phl i f = 10 ma v cc = 15 v cl = 100 pf rl = 20 k w (external) 100 t p ?propagation delay ?ns rl ?load resistance ?k w 600 400 200 30 50 800 010 20 40 t plh t phl i f = 10 ma v cc = 15 v cl = 100 pf t a = 25 ? t p ?propagation delay ?ns 0 cl ?load capacitance ?pf 800 600 400 100 1400 200 300 400 i f = 10 ma v cc = 15 v rl = 20 k w t a = 25? 200 1000 t plh t phl 1200 0 500 t p ?propagation delay ?ns 0 v cc ?supply voltage ?v 800 600 400 10 1400 15 20 25 i f = 10 ma cl = 100 pf rl = 20 k w t a = 25? 200 1000 t plh t phl 530 1200 t p ?propagation delay ?ns 100 i f ?forward led current ?ma 300 10 500 15 v cc = 15 v cl = 100 pf rl = 20 k w t a = 25? 200 400 t plh t phl 5 020 t p ?propagation delay ?ns t a ?temperature ?? 400 300 200 0 40 60 100 500 -40 -20 20 80 t plh t phl i f = 10 ma v cc = 15 v cl = 100 pf rl = 20 k w (internal) 100
1-59 figure 20. optocoupler input to output capacitance model for unshielded optocouplers. figure 19. recommended led drive circuit. figure 18. thermal derating curve, dependence of safety limiting value with case temperature per vde 0884. figure 22. led drive circuit with resistor connected to led anode (not recommended). figure 21. optocoupler input to output capacitance model for shielded optocouplers. 0.1 ? v cc = 15 v 20 k w cmos 310 w +5 v v out 100 pf + *100 pf total capacitance 8 7 6 1 3 shield 5 2 4 20 k w 8 7 6 1 3 shield 5 2 4 c ledp c ledn 20 k w 8 7 6 1 3 shield 5 2 4 c ledp c ledn c led01 c led02 20 k w 0.1 ? v cc = 15 v 20 k w cmos 310 w +5 v v out 100 pf + *100 pf total capacitance 8 7 6 1 3 shield 5 2 4 20 k w output power ?p s , input current ?i s 0 0 t s ?case temperature ?? 175 1000 50 400 125 25 75 100 150 600 800 200 100 300 500 700 900 p s (mw) i s (ma) hcnw4506 output power ?p s , input current ?i s 0 0 t s ?case temperature ?? 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 p s (mw) i s (ma) hcpl-4506 option 060 175 (230) figure 23. ac equivalent circuit for figure 22 during common mode transients. 20 k w * the arrows indicate the direction of current flow for +dv cm /dt transients. 310 w v out 100 pf + i total* v cm 8 7 6 1 3 shield 5 2 4 20 k w c ledn c led01 c led02 i cledp i f c ledp i cled01
1-60 figure 27. recommended led drive circuit for ultra high cmr. figure 24. ac equivalent circuit for figure 19 during common mode transients. figure 25. not recommended open collector led drive circuit. figure 26. ac equivalent circuit for figure 25 during common mode transients. q1 +5 v 8 7 6 1 3 shield 5 2 4 20 k w 20 k w * the arrows indicate the direction of current flow for +dv cm /dt transients. v out 100 pf + v cm 8 7 6 1 3 shield 5 2 4 20 k w c ledp c ledn c led01 c led02 i cledn* q1 +5 v 8 7 6 1 3 shield 5 2 4 20 k w 20 k w * the arrows indicate the direction of current flow for +dv cm /dt transients. ** optional clamping diode for improved cmh performance. v r < v f (off) during +dv cm /dt. v out 100 pf + v cm 8 7 6 1 3 shield 5 2 4 20 k w c ledp c ledn c led01 c led02 i cledn* 310 w + v r ** figure 28. typical application circuit. 0.1 ? 20 k w cmos 310 w +5 v v out1 i led1 v cc1 m hcpl-4506 hcpl-4506 hcpl-4506 hcpl-4506 hcpl-4506 q2 q1 -hv +hv ipm 8 7 6 1 3 shield 5 2 4 20 k w hcpl-4506 0.1 ? 20 k w cmos 310 w +5 v v out2 i led2 v cc2 8 7 6 1 3 shield 5 2 4 20 k w hcpl-4506
1-61 figure 30. waveforms for dead time calculation. figure 29. minimum led skew for zero dead time. v out1 v out2 i led2 t plh max. pdd* max. = (t plh- t phl ) max. = t plh max. - t phl min. t phl min. i led1 q1 on q2 off q1 off q2 on *pdd = propagation delay difference note: the propagation delays used to calculate pdd are taken at equal temperatures. v out1 v out2 i led2 t plh min. maximum dead time (due to optocoupler) = (t plh max. - t plh min. ) + (t phl max. - t phl min. ) = (t plh max. - t phl min. ) - (t plh min. - t phl max. ) = pdd* max. - pdd* min. t phl min. i led1 q1 on q2 off q1 off q2 on *pdd = propagation delay difference t plh max. t phl max. pdd* max. max. dead time note: the propagation delays used to calculate the maximum dead time are taken at equal temperatures. led drive circuit considerations for ultra high cmr performance without a detector shield, the dominant cause of optocoupler cmr failure is capacitive coupling from the input side of the opto- coupler, through the package, to the detector ic as shown in figure 20. the hcpl-4506, hcpl-0466 and hcnw4506 improve cmr performance by using a detector ic with an optic- ally transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the capacitive coupling between the led and the optocoupler output pins and output ground as shown in figure 21. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocoupler. the main design objective of a high cmr led drive circuit becomes keep- ing the led in the proper state (on or off) during common mode transients. for example, the recommended application circuit (figure 19), can achieve 15 kv/ m s cmr while minimizing component complexity. note that a cmos gate is recommended in figure 19 to keep the led off when the gate is in the high state. another cause of cmr failure for a shielded optocoupler is direct coupling to the optocoupler output pins through c ledo1 and c ledo2 in figure 21. many factors influence the effect and magni- tude of the direct coupling includ- ing: the use of an internal or external output pull-up resistor, the position of the led current setting resistor, the connection of the unused input package pins, and the value of the capacitor at the optocoupler output (c l ). techniques to keep the led in the proper state and minimize the effect of the direct coupling are discussed in the next two sections. cmr with the led on (cmr l ) a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by overdriving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. the recommended minimum led current of 10 ma provides adequate margin over the maximum i th of 5.0 ma (see figure 5) to achieve 15 kv/ m s cmr. capacitive coupling is higher when the internal load resistor is used (due to c ledo2 ) and an i f = 16 ma is required to obtain 10 kv/ m s cmr. the placement of the led current setting resistor effects the ability of the drive circuit to keep the led on during transients and interacts with the direct coupling to the optocoupler output. for example, the led resistor in figure 22 is connected to the anode. figure 23 shows the ac equivalent circuit for figure 22 during common mode transients. during a +dvcm/dt in figure 23, the current available at the led anode (itotal) is limited by the series resistor. the led current (i f ) is reduced from its dc value by an amount equal to the current that flows through c ledp and c ledo1 . the situation is made worse
1-62 because the current through c ledo1 has the effect of trying to pull the output high (toward a cmr failure) at the same time the led current is being reduced. for this reason, the recommended led drive circuit (figure 19) places the current set- ting resistor in series with the led cathode. figure 24 is the ac equiv- alent circuit for figure 19 during common mode transients. in this case, the led current is not reduced during a +dvcm/dt tran- sient because the current flowing through the package capacitance is supplied by the power supply. during a -dvcm/dt transient, how- ever, the led current is reduced by the amount of current flowing through c ledn . but, better cmr performance is achieved since the current flowing in c ledo1 during a negative transient acts to keep the output low. coupling to the led and output pins is also affected by the connec- tion of pins 1 and 4. if cmr is limited by perturbations in the led on current, as it is for the recom- mended drive circuit (figure 19), pins 1 and 4 should be connected to the input circuit common. however, if cmr performance is limited by direct coupling to the output when the led is off, pins 1 and 4 should be left unconnected. cmr with the led off (cmr h ) a high cmr led drive circuit must keep the led off (v f v f(off) ) during common mode transients. for example, during a +dvcm/dt transient in figure 24, the current flowing through c ledn is supplied by the parallel combination of the led and series resistor. as long as the voltage developed across the resistor is less than v f(off) the led will remain off and no common mode failure will occur. even if the led momentarily turns on, the 100 pf capacitor from pins 6-5 will keep the output from dipping below the threshold. the recommended led drive circuit (figure 19) pro- vides about 10 v of margin between the lowest optocoupler output voltage and a 3 v ipm threshold during a 15 kv/ m s transient with v cm = 1500 v. additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connec- tion in figure 24, to clamp the voltage across the led below v f(off) . since the open collector drive cir- cuit, shown in figure 25, cannot keep the led off during a +dvcm/ dt transient, it is not desirable for applications requiring ultra high cmr h performance. figure 26 is the ac equivalent circuit for figure 25 during common mode transients. essentially all the current flowing through c ledn during a +dvcm/dt transient must be supplied by the led. cmr h failures can occur at dv/dt rates where the current through the led and c ledn exceeds the input threshold. figure 27 is an alternative drive circuit which does achieve ultra high cmr performance by shunting the led in the off state. ipm dead time and propagation delay specifications the hcpl-4506, hcpl-0466 and hcnw4506 include a propagation delay difference specification intended to help designers minimize dead time in their power inverter designs. dead time is the time period during which both the high and low side power transistors (q1 and q2 in figure 28) are off. any overlap in q1 and q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. to minimize dead time the designer must consider the propagation delay characteristics of the opto- coupler as well as the characteris- tics of the ipm igbt gate drive circuit. considering only the delay characteristics of the optocoupler (the characteristics of the ipm igbt gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn-on (t phl ) and turn-off (t plh ) propagation delay specifications, preferably over the desired operating temperature range. the limiting case of zero dead time occurs when the input to q1 turns off at the same time that the input to q2 turns on. this case determines the minimum delay between led1 turn-off and led2 turn-on, which is related to the worst case optocoupler propagation delay waveforms, as shown in figure 29. a minimum dead time of zero is achieved in figure 29 when the signal to turn on led2 is delayed by (t plh max - t phl min ) from the led1 turn off. note that the propagation delays used to calcu- late pdd are taken at equal temper- atures since the optocouplers under consideration are typically mounted in close proximity to each other. (specifically, t plh max and t phl min in the previous equation are not the same as the t plh max and t phl min , over the full operating temperature range, specified in the data sheet.) this delay is the maximum value for the propagation delay difference specification which is specified at 450 ns for the hcpl-4506, hcpl- 0466 and hcnw4506 over an operating temperature range of -40 c to 100 c. delaying the led signal by the maximum propagation delay dif- ference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time occurs in the highly unlikely case where one optocoup- ler with the fastest t plh and another with the slowest t phl are in the same inverter leg. the maximum dead time in this case becomes the sum of the spread in the t plh and t phl propagation delays as shown in figure 30. the maximum dead time is also equivalent to the difference between the maximum and mini- mum propagation delay difference specifications. the maximum dead time (due to the optocouplers) for the hcpl-4506, hcpl-0466 and hcnw4506 is 600 ns (= 450 ns - (-150 ns)) over an operating temperature range of -40 c to 100 c.

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